The present invention relates to a circuit for detecting the phase of a received signal and more particularly, to a circuit for detecting the phase of a received signal that is used in a receiver that receives a digitally modulated wave transmitted under a plurality of modulations with respective different C/N ratios that are required and which detects a phase angle of a received signal.
In a broadcast receiver that receives a digitally modulated wave applied with hierarchical transmission system in which a plurality of modulations with respective different C/N ratios that are required, for example 8PSK modulation, QPSK modulation and BPSK modulation, are combined in terms of timing and a digitally modulated wave under such modulations is repeatedly transmitted in successive frames, frame synchronizing signals are captured from demodulated base band signals (hereinafter referred to as symbol stream as well), a received signal phase rotation angle at the present time point is obtained from a signal point arrangement of the captured frame synchronizing signal, and the demodulated base band signals are subjected to opposite phase rotation based on the obtained received signal phase rotation angle, thereby making the demodulated base band signals coincide with the transmitted signal phase angle so as to be in absolute phase.
A conventional received signal phase detecting circuit, as shown in FIG. 1, comprises: a modulating circuit 1; a frame synchronization detecting circuit 2; and a frame synchronizing signal generator 3; and in addition, delay circuits 41 and 42 constituting a block for detecting a received signal phase; a 0xc2x0/180xc2x0 phase rotating circuit 43; cumulative averaging circuits 45 and 46; and a received signal phase determining circuit 47 that performs phase determination of a received signal under application of a conversion table using ROM. The frame synchronization detecting circuit 2 and the frame synchronizing signal generator 3 correspond to frame synchronizing signal capturing means for capturing a frame synchronizing signal from the demodulated base band signals and the delay circuits 41 and 42 correspond to extracting means for extracting symbol streams in the period of a frame synchronizing signal from the demodulated base band signals at the timing at which the symbol streams coincide with a bit stream of the synchronizing signal captured and reproduced by the frame synchronizing signal capturing means.
The conventional received signal phase detecting circuit shown in FIG. 1 performs frequency conversion of a received digitally modulated wave to a predetermined intermediate frequency signal, supplies the intermediate frequency signal subjected to frequency conversion to the demodulating circuit 1 so as to demodulate and the demodulating circuit 1 sends out, for example, demodulated base band signals I(8) and Q(8) (hereinafter also referred to as base band signals I and Q, omitting the figures in each of the parentheses that indicates the number of bits together with the parentheses) of 8 bits that are quantized. The demodulated base band signals I(8) and Q(8) are also sent out to the frame synchronization detecting circuit 2 in order to capture a frame synchronizing signal, for example, that has been BPSK-modulated.
Description will here be made of mapping for each modulation method on the transmission side using FIGS. 2(a) to (c). FIG. 2(a) shows signal point arrangement in a case where 8PSK modulation is used as a modulation method. In the 8PSK modulation method, a digital signal of 3 bits (a, b, c) can be transmitted as 1 symbol, wherein combinations of bits that constitute 1 symbol are (0, 0, 0), (0, 0, 1), to (1, 1, 1), which are totaled in 8 ways. The digital signals each of 3 bits are converted to signal point arrangements 0 to 7 on the I-Q vector plane on the transmission side of FIG. 2(a), which conversion is generally called as 8PSK mapping.
In the example shown in FIG. 2(a), the bit sequence (0, 0, 0) is converted to a signal point arrangement xe2x80x9c0xe2x80x9d, a bit sequence (0, 0, 1) to a signal point arrangement xe2x80x9c1xe2x80x9d, a bit sequence (0, 1, 1) to a signal point arrangement xe2x80x9c2xe2x80x9d, a bit sequence (0, 1, 0) to a signal point arrangement xe2x80x9c3xe2x80x9d, a bit sequence (1, 0, 0) to a signal point arrangement xe2x80x9c4xe2x80x9d, a bit sequence (1, 0, 1) to a signal point arrangement xe2x80x9c5xe2x80x9d, a bit sequence (1, 1, 1) to a signal point arrangement xe2x80x9c6xe2x80x9d, and a bit sequence (1, 1, 0) to a signal arrangement xe2x80x9c7xe2x80x9d.
FIG. 2(b) shows signal point arrangements in a case where QPSK modulation is used as a modulation method and in the QPSK modulation method, a digital signal of 2 bits (d, e) can be transmitted as 1 symbol, wherein combinations of bits constituting the symbol are totaled in 4 ways of (0, 0), (0, 1), (1, 0) and (1, 1). In the example of FIG. 2(b), for example, a bit sequence (1, 1) is converted to xe2x80x9c1xe2x80x9d, a bit sequence (0, 1) to xe2x80x9c3xe2x80x9d, a bit sequence (0, 0) to xe2x80x9c5xe2x80x9d, and a bit sequence (1, 0) to xe2x80x9c7xe2x80x9d. It should be noted that a relation between a signal point arrangement and a arrangement number in each of other modulation methods is held in the same way as the relation in case of 8PSK modulation as a standard.
FIG. 2(c) shows signal point arrangements in a case where BPSK modulation is used as a modulation method and in the BPSK modulation method, a digital signal (f) of 1 bit is transmitted as 1 symbol. Conversion of the digital signal (f) is such that, for example, (1) is converted to a signal point arrangement xe2x80x9c0xe2x80x9d and (0) is converted to a signal point arrangement xe2x80x9c4xe2x80x9d.
Now, description will be made of a frame synchronizing signal. In the hierarchical transmission system, a frame synchronizing signal is transmitted after being subjected to BPSK modulation with the lowest C/N ratio that is required. When arrangement is such that a bit stream of a frame synchronizing signal constituted of 16 bits is (S0, S1, . . . S14, S15), wherein the bit steam is sequentially sent out from S0, and a bit stream (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0) or a bit sequence (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1), the latter of which is the former sequence whose latter half 8 bits are inverted, are alternately sent out in successive frames. Hereinafter, the symbol stream of a frame synchronizing signal is also referred to as xe2x80x9cSYNCPATxe2x80x9d or xe2x80x9cnSYNCPAxe2x80x9dT, the latter mark of which is the former symbol stream whose latter half 8 bits are inverted. The symbol streams are converted with BPSK mapping shown in FIG. 2(c) on the transmission side to a signal point arrangement xe2x80x9c0xe2x80x9d or xe2x80x9c4xe2x80x9d and the converted symbol steam is transmitted.
When it is confirmed by a demodulated base band signal in the frame synchronization detecting circuit 2 that symbol streams of frame synchronizing signals xe2x80x9cSYNCPATxe2x80x9d and xe2x80x9cnSYNCPATxe2x80x9d that, as described above, are BPSK-mapped are alternately received in a repeating manner in constant frame intervals, it is judged that frame synchronization is established and a frame synchronization pulse is output in each frame period.
In a hierarchical transmission system in which normally, a plurality of modulation methods with respective different C/N ratios that are required are combined in terms of timing and a digitally modulated wave is repeatedly transmitted in successive frames, header data indicating the multiple combinations are multiplexed and a header data indicating the multiple combinations is extracted in response to a timing signal that is generated by a frame synchronizing pulse that is output from the frame synchronization detecting circuit 2 after it is judged that the frame Synchronization has been established. As a result, it is after a frame multiple combination is known that processings for different modulation types are separately enabled.
In other words, since the demodulating circuit 1 operates as an 8PSK demodulating circuit by the time when it is judged that frame synchronization has been established, the I and Q axes of the I-Q vector plane on the reception side are subjected to phase rotation by xcex8=45xc2x0xc3x97n, where n is one of integers of n=0 to 7, as compared with those on the transmission side according to a phase state of a demodulated carrier wave reproduced in a carrier wave reproducing circuit of the demodulating circuit 1. For example, in a case of a frame synchronizing signal transmitted after being BPSK-modulated, symbol streams of the frame synchronizing signal that are BPSK-mapped such as to convert a bit xe2x80x9c1xe2x80x9d and a bit xe2x80x9c0xe2x80x9d to a signal point arrangement xe2x80x9c0xe2x80x9d and a signal point arrangement xe2x80x9c4xe2x80x9d respectively have 8 demodulated phases of the frame synchronizing signal according to a phase state of a demodulated carrier wave: a case where being arranged at signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d same as on the transmission side, a case where being arranged at signal arrangements xe2x80x9c1xe2x80x9d and xe2x80x9c5xe2x80x9d that receive phase rotation by xcex8=45xc2x0 relative to the signal point arrangements on the transmission side and a case where being arranged at signal point arrangements xe2x80x9c2xe2x80x9d and xe2x80x9c6xe2x80x9d that receive phase rotation by xcex8=90xc2x0 relative to the signal point arrangements on the transmission side.
Signals transmitted after being modulated by means of QPSK modulation and 8PSK modulation are affected by phase rotation similar to the case of PBSK modulation. When a case where the maximum number of phases of PSK modulation in which a digitally modulated wave is repeatedly transmitted in successive frames with combinations of bits in terms of timing is 8, that is a case of 8PSK modulation, is considered, there are 8 received signal phases, each of which is shifted by 45xc2x0 from the adjacent phase state.
A phase rotation angle of a received signal, however, can be obtained by comparison of a signal point arrangement of a frame synchronizing signal that is already known on the transmission side with a signal point arrangement of a frame synchronizing signal received. Description will below be made of this method of obtaining the phase rotation angle.
In the demodulating circuit 1 (see FIG. 1), a symbol stream of a frame synchronizing signal demodulated into base band signals is one that is obtained by BPSK-mapping xe2x80x9cSYNCPATxe2x80x9d or xe2x80x9cnSYNCPATxe2x80x9d constituted of a bit xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d on the transmission side and it is apparent from the respective signal point arrangements that a phase difference between the symbols of the bit xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is 180xc2x0. Therefore, when all of symbols of the bit xe2x80x9c0xe2x80x9d included in a symbol stream of a frame synchronizing signal received are subjected to 180xc2x0 phase rotation, a stream constituted of 16 symbols all with the bit xe2x80x9c1xe2x80x9d is obtained.
The average value of the obtained stream is acquired and the value is adopted as a point arrangement of a received signal for the bit xe2x80x9c1xe2x80x9d. Now, since a signal point arrangement for the bit xe2x80x9c1xe2x80x9d of BPSK is xe2x80x9c0xe2x80x9d, a received signal phase rotation angle xcex8 is obtained by comparison of the signal point arrangement of the BSPK bit with the received signal point arrangement.
Definition is here made in regard to a relation of a received signal phase rotation angle 0 and a phase rotation angle signal RT (3) that is an output of the received signal phase detecting circuit, as indicated by the following equation (1):
RT(3)=xcex8/45 xe2x80x83xe2x80x83(1)
where xcex8=nxc3x9745xc2x0 and n is one of integers of n=0 to 7.
Further description will be described based on the conventional example of FIG. 1. The frame synchronizing signal generator 3 generates a bit stream of a reproduced frame synchronizing signal corresponding to the patterns xe2x80x9cSYNCPATxe2x80x9d or xe2x80x9cnSYNCPATxe2x80x9d of a frame synchronizing signal that the generator 3 has captured in response to reception of a frame synchronizing pulse output from the frame synchronization detecting circuit 2 and the bit stream of a reproduced frame synchronizing signal is supplied to the 0xc2x0/180xc2x0 phase rotating circuit 43. The frame synchronizing signal generator 3 generates a frame synchronizing signal section signal based on the section of a frame synchronizing signal which the frame synchronizing signal generator 3 has captured and the frame synchronizing signal section signal is supplied to the delay circuits 41 and 42.
The delay circuits 41 and 42 that have received the frame synchronizing signal section signal delays a symbol stream of a frame synchronizing signal that is multiplexed into base band signals so that the symbol stream of a frame synchronizing signal that is multiplexed into the base band signals demodulated by the demodulating circuit 1 and a bit stream of a reproduced frame synchronizing signal sent out from the frame synchronizing signal generator 3 coincide with each other in the timing at the input end position of the 0xc2x0/180xc2x0 phase rotating circuit 43.
Base band signals DI(8) and DQ(8) delayed by the delay circuits 41 and 42 are input to the 0xc2x0/180xc2x0 phase rotating circuit 43. The output gates of the delay circuits 41 and 42 are opened only during a symbol stream section of a frame synchronization signal with 16 symbols by a frame synchronization signal section signal output from the frame synchronizing signal generator 3. At the input of the 0xc2x0/180xc2x0 phase rotating circuit 43, a reproduced frame synchronizing signal output from the frame synchronizing signal generator 3 and the symbol stream of the frame synchronizing signal are made to be coincide with each other in timing by the delay circuits 41 and 42 as described above.
At this point, in the case of logic xe2x80x9c0xe2x80x9d based on whether a bit in a bit stream of the reproduced frame synchronizing signal supplied is logic xe2x80x9c0xe2x80x9d or logic xe2x80x9c1xe2x80x9d, the 0xc2x0/180xc2x0 phase rotating circuit 43 outputs a corresponding symbol in a symbol stream of a frame synchronizing signal that is multiplexed into demodulated base band signals that are supplied through the delay circuits 41 and 42 after performing a 180xc2x0 phase rotation thereof, while in the case of logic xe2x80x9c1xe2x80x9d, the 0xc2x0/180xc2x0 phase rotating circuit 43 outputs a corresponding symbol in a symbol stream of a frame synchronizing signal that is multiplexed into demodulated base band signals that are supplied through the delay circuits 41 and 42 without performing any phase rotation thereof.
At the input of the 0xc2x0/180xc2x0 phase rotating circuit 43, a symbol stream of a frame synchronizing signal that is multiplexed into demodulated base band signals and a bit stream of a reproduced frame synchronizing signal sent out from the frame synchronizing signal generator 3 are made to coincide with each other in timing by the delay circuits 41 and 42. Symbol streams DI(8) and DQ(8) of a frame synchronizing signal that are output from the delay circuits 41 and 42 whose output gates are opened by a frame synchronizing signal section signal sent out from the frame synchronizing signal generator 3, in the case where a bit stream of the reproduced frame synchronizing signal is logic xe2x80x9c0xe2x80x9d, receives 180xc2x0 phase rotation and are respectively sent out to the cumulative averaging circuits 45 and 46.
FIG. 3(a) shows signal point arrangements of a frame synchronizing signal when reception is effected at a received signal phase rotation angle xcex8=0xc2x0 (absolute phase) and FIG. 3(b) shows how signal point arrangements of symbol streams VI(8) and VQ(8) after being converted in the 0xc2x0/180xc2x0 phase rotating circuit 43 are arranged. The symbol streams VI(8) and VQ(8) are respectively sent out to the cumulative averaging circuits 45 and 46, cumulative averaging is performed in a predetermined section and symbol streams AVI(8) and AVQ(8) that are summed and averaged in each predetermined section are output. The cumulative averaging is performed on the symbol streams VI(8) and VQ(8) in order that a signal point arrangement is obtained in a stable manner even when a minor change in phase and/or a change in amplitude of a received base band signal occur by deterioration in a C/N ratio in reception.
Received signal points (AVI(8) and AVQ(8)) of a BPSK-mapped signal for a bit xe2x80x9c1xe2x80x9d are obtained in the cumulative averaging circuits 45 and 46. Then, the received signal points AVI(8) and AVQ(8) are input to the received signal phase determining circuit 47 and a phase rotation angle signal RT (3) of three bits corresponding to a phase rotation angle defined by the equation (1) is obtained based on a received signal phase determination table shown in FIG. 4. In case of a received signal phase rotation angle xcex8=0xc2x0 for example, a phase rotation signal that has been determined using the received signal phase determination table with respect to signal points of AVI(8) and AVQ(8) is xe2x80x9c0xe2x80x9d. Therefore, a bit sequence (0, 0, 0) is sent out as the phase rotation angle signal RT (3). Further, in a case of a received signal phase rotation angle xcex8=45xc2x0, a phase rotation signal is xe2x80x9c1xe2x80x9d likewise and therefore, a bit sequence (0, 0, 1) is sent out as the phase rotation angle signal RT(3).
Further, in a broadcast receiver that receives a digitally modulated wave applied with the hierarchical transmission system in which a digitally modulated wave that is transmitted through a plurality of modulation methods with respective different C/N ratios that are required which modulation methods are combined in terms of timing is repeatedly transmitted in successive frames, a phase rotation angle signal RT(3) is obtained in the received signal phase detecting circuit and demodulated base band signals I(8) and Q(8) are subjected to opposite phase rotation using a phase rotation angle signal RT(3) so as to be in absolute phase.
However, when using the above described conventional received signal phase detecting circuit, if the 0xc2x0/180xc2x0 phase rotating circuit 43 is constituted of table conversion, a required memory capacity is 128 k bytes (=216xc3x9716 bits) and further if the received signal phase determining circuit 47 is constituted of table conversion, a required memory capacity is 216xc3x973 bits. In such a way, the scale of the circuits are large when the 0xc2x0/180xc2x0 phase rotating circuit 43 and the received signal phase determining circuit 47 are constituted of table conversion and thereby a problem has been arisen because of such a large scale in circuit integration.
It is an object of present invention to provide a received signal phase detecting circuit whose circuit scale is small.
A received signal phase detecting circuit recited in claim 1 of the present invention comprises:
frame synchronizing signal capturing means for capturing a frame synchronizing signal from a demodulated base band signal;
extracting means for extracting a symbol stream in the period of a frame synchronizing signal from a demodulated base band signal at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured and reproduced by the frame synchronizing signal capturing means; and
a cumulative addition/subtraction averaging circuit to which the symbol stream extracted by the extracting means is input and in which when a bit in a bit stream of the reproduced synchronizing signal is logic xe2x80x9c1xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is added, and when the bit in a bit stream of the reproduced synchronizing signal is logic xe2x80x9c0xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is subtracted and results of cumulative addition/subtraction are averaged over a predetermined period, wherein a received signal phase is determined based on an output of the cumulative addition/subtraction averaging circuit.
According to the received signal phase detecting circuit recited in claim 1 of the present invention, a frame synchronizing signal is captured from a demodulated base band signal by the synchronizing signal capturing means and a symbol stream in the period of a frame synchronizing signal is extracted by the extracting means from a demodulated base band signal at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured by the frame synchronizing signal capturing means. In the cumulative addition/subtraction averaging circuit, when a bit in a bit stream of the captured synchronizing signal is logic xe2x80x9c1xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is added, and when the bit in a bit stream of the captured synchronizing signal is logic xe2x80x9c0xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is subtracted, and results of cumulative addition/subtraction are averaged over a predetermined period. A phase of the received signal is determined based on an output from the cumulative addition/subtraction circuit.
According to a received signal phase detecting circuit recited in claim 1 of the present invention, a 0xc2x0/180xc2x0 phase rotating circuit and a cumulative averaging circuit that have been conventionally used are replaced by a cumulative addition/subtraction averaging circuit and the 0xc2x0/180xc2x0 phase rotating circuit is unnecessary, thereby reducing a circuit scale.
A received signal phase detecting circuit recited in claim 2 of the present invention comprises:
frame synchronizing signal capturing means for capturing a frame synchronizing signal from a demodulated base band signal;
extracting means for extracting a symbol stream in the period of a frame synchronizing signal from a demodulated base band signal at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured and reproduced by the frame synchronizing signal capturing means;
0xc2x0/180xc2x0 phase rotating means to which the symbol stream extracted by the extracting means is input, for outputting a corresponding symbol of the symbol stream extracted by the extracting means after performing 180xc2x0 phase rotation on the corresponding symbol when a bit of a bit stream of the reproduced synchronizing signal is logic xe2x80x9c0xe2x80x9d, and outputting a corresponding symbol of the symbol stream extracted by the extracting means after performing no phase rotation on the corresponding symbol when the bit of a bit stream of the reproduced synchronizing signal is logic xe2x80x9c1xe2x80x9d;
a cumulative averaging circuit for summing outputs from the 0xc2x0/180xc2x0 phase rotating means over a predetermined period;
a phase rotating circuit for performing phase rotation of an output from the cumulative averaging circuit by (22.5xc2x0+45xc2x0xc3x97n), where n is an integer selected from n =0 to 7; and
a phase determining circuit for determining a phase of an output from the phase rotating circuit.
According to the received signal phase detecting circuit recited in claim 2 of the present invention, a frame synchronizing signal is captured from a demodulated base band signal by the synchronizing signal capturing means and a symbol stream in the period of a frame synchronizing signal is extracted from a demodulated base band signal by the extracting means at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured by the frame synchronizing signal capturing means. With the bit stream extracted by the extracting means being received, a corresponding bit of the symbol stream extracted by the extracting means receives 180xc2x0 phase rotation when a bit of the captured synchronizing signal is logic xe2x80x9c0xe2x80x9d and is output from the 0xc2x0/180xc2x0 phase rotating means, and a corresponding symbol of the symbol stream extracted by the extracting means receives no phase rotation when the bit of the bit stream of the captured synchronizing signal is logic xe2x80x9c1xe2x80x9d and is output from the 0xc2x0/180xc2x0 phase rotating means. Outputs from the 0xc2x0/180xc2x0 phase rotating means are subjected to cumulative averaging over a predetermined period in the cumulative averaging circuit and are output therefrom, an output from the cumulative averaging circuit receives a phase rotation of (22.5xc2x0+45xc2x0xc3x97n), wherein n is an integer selected from n=0 to 7, in the phase rotating circuit and a phase of an output of the phase rotating circuit is determined by the phase determining circuit.
In this case, since a conventional received signal phase determining circuit that has table conversion using ROM is replaced with 0xc2x0/180xc2x0 phase rotating means configured by a multiplier and an adder, and a phase determining circuit of a simple configuration, a circuit scale is reduced.
A received signal phase detecting circuit recited in claim 3 of the present invention comprises:
frame synchronizing signal capturing means for capturing a frame synchronizing signal from a demodulated base band signal;
extracting means for extracting a symbol stream in the period of a frame synchronizing signal from a demodulated base band signal at the timing at which the symbol stream coincides with a bit stream of a synchronizing signal captured and reproduced by the frame synchronizing signal capturing means;
a cumulative addition/subtraction averaging circuit to which the symbol stream extracted by the extracting means is input and in which when a bit in a bit stream of the reproduced synchronizing signal is logic xe2x80x9c1xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is added, and when the bit in a bit stream of the reproduced synchronizing signal is logic xe2x80x9c0xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is subtracted and results of cumulative addition/subtraction are averaged over a predetermined period;
a phase rotating circuit for performing phase rotation of an output from the cumulative addition/subtraction averaging circuit by (22.5xc2x0+45xc2x0xc3x97n), where n is an integer selected from n=0 to 7; and
a phase determining circuit for determining a phase of an output from the phase rotating circuit.
According to the received signal phase detecting circuit recited in claim 3 of the present invention, a frame synchronizing signal is captured from a demodulated base band signal by the synchronizing signal capturing means and a symbol stream in the period of a frame synchronizing signal is extracted from a demodulated base band signal by the extracting means at the timing at which the symbol coincides with a bit stream of the synchronizing signal captured by the frame synchronizing signal capturing means. In the cumulative addition/subtraction averaging circuit, when a bit in a bit stream of the captured synchronizing signal is logic xe2x80x9c1xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is added, and when the bit in a bit stream of the captured synchronizing signal is logic xe2x80x9c0xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is subtracted, and results of cumulative addition/subtraction are averaged over a predetermined period. An output from the cumulative averaging circuit receives a phase rotation of (22.5xc2x0+45xc2x0xc3x97n), wherein n is an integer selected from n=0 to 7, in the phase rotating circuit and a phase of an output of the phase rotating circuit is determined by the phase determining circuit.
According to the received signal phase detecting circuit recited in claim 3 of the present invention, the 0xc2x0/180xc2x0 phase rotating means and the cumulative averaging circuit employed in the received signal phase detecting circuit recited in claim 2 according to the present invention are replaced with the cumulative addition/subtraction averaging circuit and the 0xc2x0/180xc2x0 phase rotating circuit is unnecessary, thereby reducing a circuit scale.
In the received signal phase detecting circuit recited in claim 3 of the present invention, a phase of a received signal may be determined in a phase determining circuit, which is arranged in a stage preceding the extracting means, based on an output of a cumulative addition/subtraction averaging circuit.
A received signal phase detecting circuit recited in claim 5 of the present invention comprises:
frame synchronizing signal capturing means for capturing a frame synchronizing signal from a demodulated base band signal;
a phase rotating circuit for performing phase rotation of a demodulated base band signal by (22.5xc2x0+45xc2x0xc3x97n), where n is an integer selected from n=0 to 7;
extracting means for extracting a symbol stream in the period of a frame synchronizing signal from a base band signal that is phase-rotated by the phase rotating circuit at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured and reproduced by the frame synchronizing signal capturing means;
code inverting means to which the symbol stream extracted by the extracting means is input, for inverting a code of a corresponding symbol in the symbol stream extracted by the extracting means to output the corresponding symbol after the inversion only when a bit in a bit stream of the reproduced synchronizing signal is logic xe2x80x9c0xe2x80x9d;
a phase determining circuit that determines a phase of an output from the code inverting means;
a gray code converter that performs gray code conversion of an output from the phase determining circuit;
majority determining means for receiving an output of the gray code converter and performing majority determination; and
a binary code converter that performs binary code conversion of an output from the majority determining means, wherein
an output from the binary code converter is adopted as a received signal phase rotation angle signal.
According to the received signal phase detecting circuit of the present invention, a frame synchronizing signal is captured from a demodulated base band signal by the synchronizing signal capturing means, the demodulated base band signal receives a phase rotation of (22.5xc2x0+45xc2x0xc3x97n), wherein n is an integer selected from n=0 to 7, by the phase rotating circuit and a symbol stream in the period of a frame synchronizing signal is extracted from the base band signal that has received phase rotation by the extracting means at the timing at which the symbol stream coincides with a bit stream of the synchronizing signal captured by the frame synchronizing signal capturing means. When the bit of a bit stream of the captured synchronizing signal is logic xe2x80x9c0xe2x80x9d, a corresponding symbol in the symbol stream extracted by the extracting means is inverted by the code inverting means, a phase of an output from the code inverting means is determined by the phase determining circuit, an output from the phase determining circuit receives code conversion to a gray code by the gray code converter, majority determination is performed on an output from the gray code converter by the majority determining means, which receives the output from the gray code converter, an output from the majority determining means receives code conversion by the binary code converter, and a phase rotation angle of a received signal is eventually determined based on an output from the binary code converter.
According to a received signal phase detecting circuit of the present invention, a 0xc2x0/180xc2x0 phase rotating circuit and a cumulative averaging circuit that have conventionally used are replaced with the 22.5xc2x0 phase rotating circuit and code inverting means and the 0xc2x0/180xc2x0 phase rotating circuit and the cumulative averaging circuit are unnecessary, thereby reducing a circuit scale.
In addition, according to a received signal phase detecting circuit of the present invention, since a circuit scale can be reduced by using majority determining circuits and two phase determination values adjacent to each other are different from each other is limited to one bit by gray-coding, therefore even in a case where there arise a minute change in phase and a change in amplitude of a received base band signal due to deterioration in a C/N ratio in reception, which has in turn entailed a false phase determination, an influence thereof can be minimized and reliability can be improved.